Conference Proceedings

  1. S. Penta et al., "Performance Evaluation of UCIe-based Die-to-Die Interface on Low-Cost 2D Packaging Technology," 2024 IEEE 74th Electronic Components and Technology Conference (ECTC), Denver, CO, USA, 2024, pp. 274-278, doi: 10.1109/ECTC51529.2024.00052. 

  2. A. Kaul, M. Manley, J. Read, Y. Luo, X. Peng, S. Yu, M. S. Bakir, “Co-optimization for robust power delivery design in 3D-heterogeneous integration of compute-in-memory accelerators,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2024, Hawaii, USA, invited.

  3. M. Manley, A. Kaul and M. S. Bakir, "Design Space Exploration for Power Delivery Network in Next Generation 3D Heterogeneous Integration Architectures," 2024 IEEE 74th Electronic Components and Technology Conference (ECTC), Denver, CO, USA, 2024, pp. 2223-2228, doi: 10.1109/ECTC51529.2024.00378.

  4. E. T. Surillo et al., "Bayesian Optimization of Large Glass Package Architecture for System-Level Reliability in High-Performance Computing Applications," 2024 IEEE 74th Electronic Components and Technology Conference (ECTC), Denver, CO, USA, 2024, pp. 246-253, doi: 10.1109/ECTC51529.2024.00047.

  5. R. Sahay et al., "Inverse Hybrid Bonding with Metal Oxide Framework as Infill for Heterogeneous Integration," 2024 IEEE 74th Electronic Components and Technology Conference (ECTC), Denver, CO, USA, 2024, pp. 1837-1840, doi: 10.1109/ECTC51529.2024.00307

  6. C. -H. Kuo et al., "Co Metal ALD on Cu with Cyclic Clean by Peroxide and Hydrazine for Inverse Hybrid Metal Bonding," 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), HsinChu, Taiwan, 2024, pp. 1-2, doi: 10.1109/VLSITSA60681.2024.10546373.

  7. J. Sharda, M. Manley, A. Kaul, W. Li, M. Bakir and S. Yu, "Design and Thermal Analysis of 2.5D and 3D Integrated System of a CMOS Image Sensor and a Sparsity-Aware Accelerator for Autonomous Driving," in IEEE Journal of the Electron Devices Society, doi: 10.1109/JEDS.2024.3354621

  8. M. A. Nieves Calderon, S. Oh, J. R. Brescia and M. S. Bakir, "Multi-Chiplet Implementation of a Replaceable Integrated Chiplet (PINCH) Assembly," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 14, no. 3, pp. 529-532, March 2024, doi: 10.1109/TCPMT.2024.3363652

  9. S. Yu, T. K. Gaylord and M. S. Bakir, "Scalable Fiber-Array-to-Chip Interconnections with Sub-Micron Alignment Accuracy," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 748-752, doi: 10.1109/ECTC51909.2023.00130.

  10. A. Kaul, M. O. Hossen, M. Manley and M. S. Bakir, "Design Considerations for Power Delivery Network and Metal-Insulator-Metal Capacitor Integration in Bridge-Chips for 2.5-D Heterogeneous Integration," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 985-990.​

  11. M. Manley et al., "Towards Selective Cobalt Atomic Layer Deposition for Chip-to-Wafer 3D Heterogeneous Integration," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 374-378.

  12. A. Victor, M. Manley, S. Oh and M. S. Bakir, "Reconstituted-SiO2 Tier with Integrated Copper Heat Spreader," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 1767-1772, doi: 10.1109/ECTC51909.2023.00302.

  13. J. Sharda, M. Manley, A. Kaul, W. Li, M. Bakir, S. Yu, “Thermal modeling of 2.5D integrated package of CMOS image sensor and FPGA for autonomous driving,” IEEE Electron Devices Technology and Manufacturing Conference (EDTM) 2023, Seoul, Korea.

  14. T. Zheng, M. Manley and M. Bakir, "Embedded mm-Wave Chiplet Based Module using Fused-Silica Stitch-Chip Technology: RF Characterization and Thermal Evaluation," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, May 2023, pp. 1493-1498.

  15. M. A. Nieves Calderon, J. R. Brescia, and M. S. Bakir, "Multi-Chiplet Implementation of a Replaceable Integrated Chiplet (PINCH) Assembly to Facilitate Heterogeneous Integration", Government Microcircuit Applications & Critical Technology Conf., San Diego, CA, Mar. 2023

  16. A. Victor, M. Manley, S. Oh and M. S. Bakir, "Reconstituted-SiO2 Tier with Integrated Copper Heat Spreader," in Proceedings of SRC TECHCON 2022, Austin, TX, USA, 2022.

  17. J. Lu, M. Zia, M. J. Williams, A. L. Jacob, B. Chung, S. J. Sober and M. S. Bakir, "High-performance Flexible Microelectrode Array with PEDOT:PSS Coated 3D Micro-cones for Electromyographic Recording", in 44th International Engineering in Medicine and Biology Conference, Glasgow, United Kingdom, Jul. 2022.

  18. T. Zheng and M. S. Bakir, “Fused-Silica Stitch-Chips with Compressible Microinterconnects for Embedded RF/mm-wave Chiplets”, in 2022 IEEE/MTT-S International Microwave Symposium (IMS), Denver, CO, Jun. 2022.

  19. M. Manley, A. Kaul, M. -J. Li and M. S. Bakir, "Ultra-Dense 3D Polylithic Integration Technology", Government Microcircuit Applications & Critical Technology Conf., Miami, FL, Mar. 2022.

  20. J. R. Brescia, J. L. Gonzalez, T. Zheng and M. S. Bakir, "Replaceable Integrated Chiplet (PINCH) Assembly for Heterogeneous Integration", Government Microcircuit Applications & Critical Technology Conf., Miami, FL, Mar. 2022.

  21. Y. Wang, C. Swank, T. Zheng, J. F. Buckwalter, A. Kummel, M. Rodwell and M. S. Bakir, “Interposer and Advanced Packaging Enabled by Ultra-Dense Microdiamond Composites for RF/mm-wave Applications”, in Proceeding of TECHCON 2021, Sep. 2021.

  22. S. Kochupurackal Rajan, A. Kaul, T Sarvey, G. S. May, and M. S. Bakir, "Design Considerations, Demonstration, and Benchmarking of Silicon Micro-cold Plate and Monolithic Microfluidic Cooling for 2.5D ICs," 71st IEEE Electronic Components and Technology Conf. (ECTC),  Jun. 2021.

  23. X. Peng , W. Chakraborty, A. Kaul, W. Shim, M.S. Bakir, S. Datta, S. Yu, "Benchmarking Monolithic 3D Integration for Compute-in-Memory Accelerators: Overcoming ADC Bottlenecks and Maintaining Scalability to 7nm or Beyond," in Proc. IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2020.

  24. A. Kaul, X. Peng, S. Kochupurackal Rajan, S. Yu, and M.S. Bakir, "Thermal Modeling of 3D Polylithic Integration and Implications on BEOL RRAM Performance," in Proc. IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2020. (invited)

  25. R. Saligram, A. Kaul, A. Raychowdhury, and M.S. Bakir, "A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration," in Proc. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), virtual, Salt Lake City, UT, Oct. 2020.

  26. T. Zheng, P. K. Jo, S. Kochupurackal Rajan, and M. S. Bakir, "Polylithic integration for RF/mm-wave chiplets using stitch-chips: modeling, fabrication, and characterization," 2020 IEEE MTT-S International Microwave Symposium (IMS), Los Angeles, CA, Jun. 2020.

  27. A. Kaul, S. Kochupurackal Rajan, M. O. Hossen, G. S. May, and M. S. Bakir, "BEOL-Embedded 3D Polylithic Integration: Thermal and Interconnection Considerations," 70th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2020.

  28. J. L. Gonzalez, T. Zheng, S. Kochupurackal Rajan, and M. S. Bakir, “Package Testing using a Socketed Heterogeneous 2.5D/3D Integration Module (SHIM) for mm-wave Applications,” Proceedings of the 2020 GOMAC-Tech – Government Microcircuit Applications and Critical Technology Conference, 2020.

  29. S. Kochupurackal Rajan, M. Li, G.S. May, and M.S. Bakir, "High density and low-temperature interconnection enabled by mechanical self-alignment and electroless plating" in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Sendai, Japan, Oct. 2019.

  30. P. K. Jo, T. Zheng, and M. S. Bakir, "Polylithic Integration of 2.5D and 3D Chiplets Using Interconnect Stitching," in Proc. 69th IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May. 2019.

  31. M. Zia, B. Chung, S. J. Sober and M.S. Bakir, "Fabrication and Characterization of 3D Multi-Electrode Array on Flexible Substrate for In Vivo EMG Recording from Expiratory Muscle of Songbird," in Proc. IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2018.

  32. P. K. Jo, T. Zheng, and M. S. Bakir, "Multi-Die Polylithic Integration Enabled by Heterogeneous Interconnect Stitching Technology (HIST)," in 27th IEEE Conf. on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, Oct. 2018.

  33. M. O. Hossen, Y. Zhang, and M. Bakir, "Thermal-Power Delivery Network Co-analysis for Multi-Die Integration", in 27th IEEE Conf. on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, Oct. 2018.

  34. P. K. Jo, M. O. Hossen, X. Zhang, Y. Zhang, and M. S. Bakir, "Heterogeneous Multi-Die Stitching: Technology Demonstration and Design Considerations," in Proc. 68th IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May. 2018.

  35.  P. Yeon, J. L. Gonzalez, M. Zia, S. Kochupurackal Rajan, G. S. May, M. S. Bakir, and M. Ghovanloo, "Microfabrication, Assembly, and Hermetic Packaging of mm-Sized Free-Floating Neural Probes," in Proc. IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, Oct. 2017.

  36.  P. K. Jo, M. Zia, J. L. Gonzalez, and M. S. Bakir, "Dense and highly elastic compressible microinterconnects (CMIs) for electronic microsystems," in Proc. 67th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May. 2017.

  37.  H. Oh, X. Zhang, P. K. Jo, G. S. May, and M. S. Bakir, "Monolithic-like heterogeneously integrated microsystems using dense low-loss interconnects," in Proc. IEEE Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Phoenix, AZ, Jan. 2017. (invited).

  38. Y. Zhang, X. Zhang, W. Wahby, and M. S. Bakir, "Design considerations for 2.5-D and 3-D integration accounting for thermal constraints," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Nov. 2016.

  39.  W. Wahby, T. E. Sarvey, H. Sharma, H. Esmaeilzadeh, and M. S. Bakir, "The impact of 3D stacking on GPU-accelerated deep neural networks an experimental study," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Nov. 2016.

  40.  C. Wan, T. K. Gaylord, and M. S. Bakir, "Grating design for 3-D interconnections of waveguides in overlaid chips using the RCWA-EIS method," in Frontiers in Optics, Rochester, NY, Oct. 2016.

  41. W. Wahby and M. S. Bakir, "Impact of Alternate Metals on Routing in Scaled Monolithic 3DICs," in Proc. SRC Techcon, Austin, TX, Sep. 2016.

  42. Y. Zhang, T. E. Sarvey, Y. Zhang, M. Zia and M. S. Bakir, "Numerical and experimental exploration of thermal isolation in 3D systems using air gap and mechanically flexible interconnects," in IEEE International Interconnect Technology Conf. / Advanced Metallization Conf. (IITC/AMC), San Jose, CA, May. 2016.

  43. R. Abbaspour, D. C. Woodrum, P. A. Kottke, T. E. Sarvey, C. E. Green, Y. K. Joshi, A. G. Fedorov, S. K. Sitaraman, and M. S. Bakir, "Combined finned microgap with dedicated extreme-microgap hotspot flow for high performance thermal management," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.

  44. X. Zhang,  M. H. Nasr, D. C. Woodrum, C. E. Green, P. A. Kottke, T. E. Sarvey, Y. K. Joshi, S. K. Sitaraman, A. G. Fedorov, and M. S. Bakir, "Design, microfabrication and thermal characterization of the hotspot cooler testbed for convective boiling experiments in extreme-micro-gap with integrated micropin-fins and heat Loss minimization," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.

  45. P. Asrar, X. Zhang, C. E. Green, P. A. Kottke, T. E. Sarvey, A. G. Fedorov, M. S. Bakir, and Y. K. Joshi, "Flow boiling of R245fa in a microgap with integrated staggered pin fins," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.

  46. H. Oh, X. Zhang, G. May, and M. Bakir, "High-frequency analysis of embedded microfluidic cooling within 3-D ICs using a TSV testbed," in Proc. 66th IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May. 2016.

  47. P. Asrar, X. Zhang, C. E. Green, P. A. Kottke, T. E. Sarvey, A. G. Fedorov, M. S. Bakir, Y. K. Joshi, "Flow visualization of two phase flow of R245fa in a microgap with integrated staggered pin fins," in Thermal Measurement, Modeling & Management Symposium (SEMI-THERM), San Jose, CA, Mar. 2016.

  48. D. C. Woodrum, X. Zhang, P. A. Kottke, Y. K. Joshi, A. G. Fedorov, M. S. Bakir, and S. K. Sitaraman, "Reliability assessment of hydrofoil-shaped micro-pin fins subjected to high performance coolant," in IEEE The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.

  49. M. H. Nasr, C. E. Green, P. E. Kottke, X. Zhang, T. E. Sarvey, Y. K. Joshi, M. S. Bakir, A. G. Fedorov, "Extreme-microgap based hotspot thermal management with refrigerant flow boiling," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.

  50. Y. Song, R. Abbaspour, M. S. Bakir, and S. K. Sitaraman, "Thermal annealing effects on copper microstructure in Through-Silicon-Vias," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.

  51.  M. Zia, T. Chi, C. Zhang, P. Thadesar, T. Hookway, J. Gonzalez, T. McDevitt, H. Wang, and M. S. Bakir, "A microfabricated electronic microplate platform for low-cost repeatable bio-sensing applications," in Proc. IEEE International Electron Devices Meeting (IEDM), Washington, DC, Dec. 2015.

  52. T. E. Sarvey, Y. Zhang, L. Zheng, P. Thadesar, R. Gutala, C. Cheung, A. Rahman, M. S. Bakir, "Embedded cooling technologies for densely integrated electronic systems," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Oct. 2015. (invited)

  53. . M. Zia, C. Zhang, P. Thadesar, T. Hookway, T. Chi, J. Gonzalez, T. McDevitt, H. Wang,  and M. S. Bakir, "Fabrication of and cell growth on silicon membranes with high density TSVs for bio-sensing applications," in Proc. IEEE Biomedical Circuits and Systems Conference (BioCAS), Atlanta, GA, Oct. 2015.

  54. X. Zhang, V. Kumar, R. Alapati, A. Naeemi and M. S. Bakir, "Interconnect performance in 3D ICs accounting TSV frequency-dependent capacitance and resistive on-chip wires: model, fabrication, and testing," in Proc. SRC Techcon, Austin, TX, Sep. 2015.

  55. . H. Oh, G. May, and M. Bakir, "Silicon interposer platform with low-loss through-silicon vias using air," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Sendai, Japan, Aug. 2015.

  56. C. E. Green, P. E. Kottke, T. E. Sarvey, A. G. Federov, Y. Joshi, M. S. Bakir, "Performance and integration implications of addressing localized hotspots through two approaches: clustering of micro pin-fins and dedicated microgap coolers," in Proc. Int. Tech. Conf. and Expo. Packaging and Integration of Electronic and Photonic Microsystems and Int. Conf. Nanochannels, Microchannels, and Minichannels (InterPACKICNMM), San Francisco, CA, July 2015.

  57. . X. Zhang, X. Han, T. E. Sarvey, C. E. Green, P. A. Kottke, A. G. Fedorov, Y. Joshi, and M. S. Bakir, "3D IC with embedded microfluidic cooling: technology, thermal performance, and electrical implications," in Proc. Int. Tech. Conf. and Expo. Packaging and Integration of Electronic and Photonic Microsystems and Int. Conf. Nanochannels, Microchannels, and Minichannels (InterPACKICNMM), San Francisco, CA, July 2015.

  58. P. Thadesar and M. Bakir, "Fabrication and characterization of mixed-signal polymer-enhanced silicon interposer featuring photodefined coax TSVs and high-Q inductors," in Proc. 65th IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May 2015.

  59. L. Zheng, Y. Zhang, X. Zhang, and M. Bakir, "Silicon interposer with embedded microfluidic cooling for high-performance computing systems," in Proc. 65th IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May 2015.

  60. D. C. Woodrum, T. Sarvey, M. S. Bakir and S. K. Sitaraman, "Reliability study of micro-pin fin array for on-chip cooling," in Proc. 65th IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May 2015.

  61. Y. Zhang, T. E. Sarvey, and M. S. Bakir, "Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Cork, Ireland, Dec. 2014.

  62. C. Zhang, P. Thadesar, M. Zia, T. E. Sarvey, and M. S. Bakir, "Au-NiW mechanically flexible interconnects (MFIs) for rematable 3D integration," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Cork, Ireland, Dec. 2014.

  63. W. Wahby, L. Zheng, Y. Zhang, and M. Bakir, "A virtual integration platform for 3DIC design space exploration," in Proc. SRC Techcon, Austin, TX, Sep. 2014.

  64. H. Oh, Y. Zhang, L. Zheng, and M. Bakir,"Electrical interconnect and microfluidic cooling within 3D ICs and silicon interposer," in Proc. Int. Tech. Conf. and Expo. Packaging and Integration of Electronic and Photonic Microsystems and Int. Conf. Nanochannels, Microchannels, and Minichannels (InterPACKICNMM), Chicago, IL, Aug. 2014.

  65. P. Thadesar, L. Zheng, and M. Bakir, "Low-loss silicon interposer for three-dimensional system integration with embedded microfluidic cooling," in Proc. IEEE VLSI Technology Symposium, Honolulu, HI, June 2014.

  66. C. Zhang, H.S. Yang, M. Bakir, "Mechanically flexible interconnects with highly scalable pitch and large stand-off height for silicon interposer tile and bridge interconnection," in Proc. 64th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2014.

  67. T. E. Sarvey, Y. Zhang, Y. Zhang, H. Oh, and M. S. Bakir, "Thermal and electrical effects of staggered micropin-fin dimensions for cooling of 3D microsystems,"in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Orlando, FL, May 2014.

  68. H. S. Yang, C. Zhang, M. Zia, L. Zheng, M. Bakir, "Interposer-to-interposer electrical and silicon photonic interconnection platform using silicon bridge," in Proc. IEEE Photonics Society Optical Interconnects Conf., Coronado, CA, May 2014.

  69. S. A. Isaacs, Y. Joshi, Y. Zhang, M. Bakir, and Y. J. Kim, "Two-phase flow and heat transfer in pin-fin enhanced micro-gaps with non-uniform heating," in Proc. ASME Int. Conf. on Micro/Nanoscale Heat and Mass Transfer, Hong Kong, China, Dec. 2013.

  70. Y. Zhang, H. Oh, and M. Bakir, "Within-tier cooling and thermal isolation technologies for heterogeneous 3D ICs," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Oct. 2013.

  71. W. Wahby, A. Dembla, and M. Bakir, "Evaluation of 3DICs and fabrication of monolithic interlayer vias," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Oct. 2013.

  72. Best in Session Paper Award: P. Thadesar and M. Bakir "Fabrication and wideband characterization of novel photodefined polymer-embedded vias for silicon interposers," in Proc. SRC TECHCON, Austin, TX, Sep. 2013.

  73. H. Oh, A. Dembla, Y. Zhang, and M. Bakir "High aspect ratio TSVs in micro-pinfin heat sinks for 3D ICs," in Proc. SRC TECHCON, Austin, TX, Sep. 2013.

  74. P. Thadesar, A. Dembla, D. Brown, and M. S. Bakir, "Novel through-silicon via technologies for 3D system integration," in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.

  75. V. Kumar, L. Zheng, M. Bakir, and A. Naeemi, "Compact modeling and optimization of fine-pitch interconnects for silicon interposers", in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.

  76. J. M. Gu, P. Thadesar, A. Dembla, S. J. Hong, M. S. Bakir, and G. May, "Endpoint detection using optical emission spectroscopy in TSV fabrication," in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.

  77. Y. Zhang, L. Zheng, and M. Bakir, "Tier-independent microfluidic cooling for heterogeneous 3D ICs with nonuniform power dissipation," in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.

  78. P. Thadesar, J. M. Gu, A. Dembla, S. J. Hong, G. S. May and M. S. Bakir, "Novel photodefined polymer-clad through-silicon via technology integrated with end point detection using optical emission spectroscopy," in Proc. 24th Annual SEMI Advanced Semiconductor Manufacturing Conf. (ASMC), Saratoga Springs, NY, May 2013.

  79. L. Zheng, Y. Zhang and M. Bakir, "Design, fabrication and assembly of novel electrical and microfluidic I/Os for 3-D chip stack and silicon interposer," in Proc. 63rd IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May 2013.

  80. H.S. Yang, C. Zhang, M.S. Bakir, "A low-cost self-alignment structures for heterogeneous 3D integration," in Proc. 63rd IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May 2013.

  81. P. Thadesar and M. Bakir, "Fabrication and characterization of novel photodefined polymer-enhanced through-silicon vias for silicon interposers," in Proc. 63rd IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May 2013.

  82. P. Thadesar and M. Bakir, "Novel low-loss photodefined electrical TSVs for silicon interposers," Topical Workshop on Advanced 3D Packaging, 9th IMAPS Int. Conf. and Exhibition on Device Packaging, Scottsdale/Fountain Hills, AZ, Mar. 2013.

  83. P. Thadesar and M. Bakir, "Silicon interposer featuring novel electrical and optical TSVs," in Proc. ASME International Mechanical Engineering Congress and Exposition, Houston, TX, Nov. 2012.

  84. A. Dembla, Y. Zhang, and M. Bakir, "Fine pitch TSV integration in silicon micropin-fin heat sinks for 3D ICs," in Proc. SRC TECHCON, Austin, TX, Sep. 2012.

  85. L. Zheng and M. Bakir, "Electrical and fluidic microbumps and interconnects for 3D-IC and silicon interposer," in Proc. IEEE International System-on-Chip Conf. (SoCC), 2012.

  86. A. Dembla, Y. Zhang, and M. Bakir, "High aspect ratio TSVs in micropin-fin heat sinks for 3D ICs," in Proc. IEEE Int. Conf. Nanotechnology, Birmingham, England, Aug. 2012.

  87. S. A. Isaacs, Yoon Jo Kim, A. J. McNamara, Y. Joshi, Y. Zhang and M. S. Bakir, "Two-phase flow and heat transfer in pin-fin enhanced micro-gaps," 13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, San Diego, CA, 2012, pp. 1084-1089.

  88. A. Dembla, Y. Zhang, and M. Bakir, "Fine pitch TSV integration in silicon micropin-fin heat sinks for 3D ICs," in Proc. IEEE International Interconnect Technology Conf. (IITC), San Jose, CA, June 2012.

  89. G. Huang, M. Bakir, A. Naeemi, and J. Meindl, "Power delivery for 3-D chip stacks: physical modeling and design implication," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 2, no. 5, pp. 852-859, May 2012.

  90. C. Zhang, H. S. Yang, and M. Bakir, "Gold passivated mechanically flexible interconnects (MFIs) with high elastic deformation," in Proc. 62nd IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, 2012.

  91. Y. Zhang, A. Dembla, Y. Joshi, and M. Bakir, "3D stacked microfluidic cooling for high-performance 3D ICs" in Proc. 62nd IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, 2012.

  92. L. Zheng, G. Huang, and M. Bakir, "Power delivery and thermal management for high-performance 3D chip stack," in SRC Techcon, Austin, TX, Sep. 2011.

  93. A. Dembla, D. Brown, and M. Bakir, "Nanofabrication of ultra high density nanoscale TSVs," in SRC Techcon, Austin, TX, Sep. 2011.

  94. H. S. Yang and M. Bakir, "Design and wafer-level fabrication of positive self-alignment structures for improved vertical optical coupling," in IMAPS/IEEE-CPMT Advanced Technology Workshop on Optoelectronic Packaging, Irvine, CA, June 2011.

  95. A. Dembla, D. Brown, and M. Bakir, "Nanofabrication of high aspect ratio nanoscale TSVs," in Proc. Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN), Las Vegas, NV, May. 2011.

  96. M. Parekh, P. Thadesar and M. Bakir, "Electrical, optical, and fluidic through-silicon vias for silicon interposer applications," in Proc. 61st IEEE Electronic Components and Technology Conf., Lake Buena Vista, FL, May 2011.

  97. Y. Zhang, C. King, J. Zaveri, Y. J. Kim, V. Sahu, Y. Joshi, and M. Bakir, "Coupled electrical and thermal 3D IC centric microfluidic heat sink design and technology," in Proc. 61st IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2011.

  98. M. Bakir, P. Thadesar, C. King, J. Zaveri, H. Yang, C. Zhang, Y. Zhang, "Revolutionary innovation in system interconnection: A new era for the IC," in Proc. Photonics West, Proc. of SPIE, Feb. 2011.

  99. H. S. Yang and M. Bakir, "3D integration of CMOS and MEMS using MFI and TSV," in Proc. SRC Techcon, 2010.

  100. Y. Zhang, J. Zaveri, C. King, and M. Bakir, "Coupled electrical and thermal 3D IC centric microfluid heat sink design," in Proc. SRC Techcon, 2010.

  101. H. S. Yang and M. Bakir, "3D integration of CMOS and MEMS using mechanically flexible interconnects (MFI) and through silicon vias (TSV)," in Proc. IEEE Electronic Components and Technol. Conf., pp. 822-828, 2010.

  102. R. Ravindran, J. A. Sadie, K. E. Scarberry, H. S. Yang, M. S. Bakir, J. F. McDonald, and J. D. Meindl, "Biochemical sensing with an arrayed silicon nanowire platform," in Proc. IEEE Electronic Components and Technol. Conf., pp. 1015-1020, 2010.

  103. H. S. Yang, R. Ravindran, M. S. Bakir, J.D. Meindl, "A 3D interconnect system for large biosensor array and CMOS signal-processing IC integration," IEEE Interconnect Technology Conf. (IITC), 2010 International, 6-9 June 2010

  104. C. King, J. Zaveri, M. Bakir, and J. Meindl, "Electrical and fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs," in Proc. IEEE Electronic Components and Technology Conf., pp. 822-828, 2010.

  105. H. S. Yang and M. Bakir, "Interconnect technologies for 3D integration of CMOS and MEMS," in Proc. MRS Spring Meeting, 2010. (invited)

  106. J. Zaveri, C. King Jr., H.S. Yang, M.S. Bakir, "Wafer level batch fabrication of silicon microchannel heat sinks and electrical through silicon vias for 3D ICs," IMAPS 42nd International Symposium on Microelectronics, 2009.

  107. C. King, J. Zaveri, H. S. Yang, M. Bakir, and J. Meindl "Electro-fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs," in Proc. SRC TECHCON, 2009.

  108. J. Zaveri, C. King, H. Yang, and M. Bakir, "Wafer level batch fabrication of silicon microchannel heat sinks and electrical through silicon vias" in Proc. SRC TECHCON, 2009.

  109. M. Bakir and G. Huang, “Power Delivery, Signaling and Cooling for 3D Integrated Systems,” MRS Proceedings, vol. 1156, Jan. 2009.

  110. M. S. Bakir, C. King, D. Sekar, and B. Dang, “Electrical, optical, and fluidic interconnect networks for 3D heterogeneous integrated systems,” 2008 IEEE Avionics, Fiber-Optics and Photonics Technology Conference, Sep. 2008.

  111. M. S. Bakir, C. King, D. Sekar, H. Thacker, B. Dang, G. Huang, A. Naeemi, and J. D. Meindl, “3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation,” 2008 IEEE Custom Integrated Circuits Conference, Sep. 2008.

  112. C. King, D. Sekar, M. Bakir, B. Dang, J. Pikarsky, and J. Meindl, "3D stacking of chips with electrical and microfluidic I/O interconnects," in Proc. SRC TECHCON, 2008.

  113. D. Sekar, C. King, B. Dang, T. Spencer, H. Thacker, P. Joseph, M. Bakir, and J. Meindl, “A 3D-IC Technology with Integrated Microchannel Cooling,” 2008 International Interconnect Technology Conference, Jun. 2008.

  114. C. R. King, D. Sekar, M. S. Bakir, B. Dang, J. Pikarsky, and J. D. Meindl, “3D stacking of chips with electrical and microfluidic I/O interconnects,” 2008 58th Electronic Components and Technology Conference, May 2008.

  115. G. Huang, M. Bakir, A. Naeemi, H. Chen, and J. D. Meindl, “Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication,” 2007 IEEE Electrical Performance of Electronic Packaging, Oct. 2007.

  116. M. S. Bakir, B. Dang, and J. D. Meindl, “Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems,” 2007 IEEE Custom Integrated Circuits Conference, Sep. 2007.

  117. M. S. Bakir, B. Dang, and J. D. Meindl, “Electrical, Optical and Thermofluidic Chip I/O Interconnections,” ASME 2007 InterPACK Conference, Volume 1, Jul. 2007.

  118. C. King, D. Sekar, M. Bakir, B. Dang, J. Pikarsky, J. Meindl, "Assembly techniques for microfluidic networks in three-dimensional integrated circuits," SRC TECHCON, 2007.

  119. M. Bakir and J. Meindl, "Fully compatible low cost electrical, optical, and fluidic I/O interconnect networks for ultimate performance 3D gigascale systems," in Proc. Int. 3D System-in-Chip Conf., 2007. (invited, Tokyo,  Japan)

  120. M. Bakir, B. Dang, G. Huang, and J. Meindl, "Limits and opportunities for heat removal and power delivery to gigascale systems," in Proc. SEMATECH Thermal and Design Issues in 3D ICs, 2007. (invited) Paper featured in multiple trade journal articles.

  121. M. S. Bakir, B. Dang, O. O. Ogunsola, and J. D. Meindl, “‘trimoda’ Wafer-Level Package: Fully Compatible Electrical, Optical, and Fluidic Chip I/O Interconnects,” 2007 Proceedings 57th Electronic Components and Technology Conference, May 2007.

  122. M. S. Bakir, P. A. Kohl, A. L. Glebov, E. Elce, D. Bhusari, M. G. Lee, and J. D. Meindl, “Flexible polymer pillars for optical chip assembly: materials, structures, and characterization,” Photonics Packaging, Integration, and Interconnects VII, Feb. 2007.

  123. H. Thacker, O. Ogunsola, A. Carson, M. Bakir, and J. Meindl, “Optical Through-Wafer Interconnects for 3D Hyper-Integration,” LEOS 2006 - 19th Annual Meeting of the IEEE Lasers and Electro-Optics Society, Oct. 2006.

  124. K.-N. Chen, M. Bakir, J. Meindl, and R. Reif, "Copper interconnect bonding for polymer pillar I/O interconnects and three-dimensional (3D) integration applications," in Proc. TMS Electronics Materials Conf., 2006.

  125. O. Ogunsola, H. Thacker, B. Bachim, M. Bakir, T. Gaylord, and J. Meindl, “Polymer Pillars as Optical I/O for Gigascale Chips using Mirror-Terminated Waveguides,” 2006 International Interconnect Technology Conference, Jun. 2006.

  126. M. S. Bakir, B. Dang, H. D. Thacker, O. O. Ogunsola, R. Ogra, and J. Meindl, “Dual-Mode Electrical-Optical Flip-Chip I/O Interconnects and a Compatible Probe Substrate for Wafer-Level Testing,” 56th Electronic Components and Technology Conference 2006, May 2006.

  127. A. He, M. S. Bakir, S. Ann, B. Allen, and P. Kohl, “Fabrication of Compliant, Copper-Based Chip-to-Substrate Connections,” 56th Electronic Components and Technology Conference 2006, May 2006.

  128. B. Dang, P. Joseph, M. Bakir, P. Kohl, J. Meindl, "Fabrication, assembly and testing of an on-chip microfluidic heat sink," in Proc. Int. Symp. of Microelectronics, 2005, TP2:pp.1-5.

  129. H. Thacker, O. Ogunsola, M. Bakir, and J. Meindl, “Probe Module for Wafer-Level Testing of Gigascale Chips With Electrical and Optical I/O Interconnects,” Advances in Electronic Packaging, Parts A, B, and C, Jul. 2005.

  130. B. Dang et al., "A Chip-Scale Cooling Scheme With Integrated Heat Sink and Thermal-Fluidic I/O Interconnects," in ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference, 2005, vol. Advances in Electronic Packaging, Parts A, B, and C, pp. 605-610, doi: 10.1115/ipack2005-73416.

  131. B. Dang, P. J. Joseph, X. Wei, M. S. Bakir, P. A. Kohl, Y. K. Joshi, and J. D. Meindl, “A Chip-Scale Cooling Scheme With Integrated Heat Sink and Thermal-Fluidic I/O Interconnects,” in Proc. ASME InterPACK, Jul. 2005.

  132. B. Dang, P. Joseph, M. Bakir, T. Spencer, P. Kohl, and J. Meindl, “Wafer-level microfluidic cooling interconnects for GSI,” Proceedings of the IEEE 2005 International Interconnect Technology Conference, Jun. 2005.

  133. H. Thacker, O. Ogunsola, M. Bakir, and J. Meindl, “High-density probe substrate for testing optical interconnects,” Proceedings of the IEEE 2005 International Interconnect Technology Conference, Jun. 2005.

  134. H. Thacker, O. Ogunsola, M. Bakir, and J. Meindl, "Probe module for wafer-level testing of gigascale chips with polymer pillar-based electrical and optical I/O interconnects," in Proc. SRC TECHCON, 2005.

  135. B. Dang, P. J. Joseph, M. S. Bakir, P. A. Kohl, Y. K. Joshi, and J. D. Meindl, "A chip-scale cooling scheme with on-chip heat sink and integrated microfluidic I/O interconnects," in Proceedings SRC TECHCON, 2005.

  136. O. Ogunsola, H. Thacker, B. Bachim, M. Bakir, T. Gaylord, J. Meindl, "Mirror-enabled polymer pillar optical I/O interconnects for gigascale integration," in Proc. SRC TECHCON, 2005.

  137. B. Dang, M. Bakir, K. Martin, and J. Meindl, "Assembly and reliability assessment of Sea-of-Leads compliant wafer level package," in Proceedings IMAPS International Symposium on Microelectronics, 2004, pp 7-14.

  138. M. Bakir, and J. D. Meindl, "Wafer-level packaging of optoelectronic chips using sea of leads electrical and optical I/O interconnections," in The 17th Annual Meeting of the IEEELasers and Electro-Optics Society, 2004: IEEE, pp. 583-584.

  139. K. Shakeri, M. Bakir, and J. D. Meindl, "Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution," in IEEE International SOC Conference, 2004. Proceedings., 2004: IEEE, pp. 78-81.

  140. B. Dang, C. Patel, H. Thacker, M. Bakir, K. Martin, and J. Meindl, "Optimal implementation of sea of leads (SoL) compliant interconnect technology," in Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No. 04TH8729), 2004: IEEE, pp. 99-101.

  141. M. S. Bakir and J. D. Meindl, "Integrated electrical, optical, and thermal high density and compliant wafer-level chip I/O interconnections for gigascale integration," in 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No. 04CH37546), 2004, vol. 1: IEEE, pp. 1-6.

  142. M. S. Bakir et al., "Chip integration of sea of leads compliant I/O interconnections for the ultimate enabling of chips with low-k interlayer dielectrics," in 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No. 04CH37546), 2004, vol. 1: IEEE, pp. 1167-1173.

  143. M. S. Bakir et al., "Sea of polymer pillars: Dual-mode electrical-optical input/output interconnections," in Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No. 03TH8695), 2003: IEEE, pp. 77-79.

  144. M. S. Bakir, T. Gaylord, P. Kohl, K. Martin, and J. Meindl, "Sea of dual mode polymer pillar I/O interconnections for gigascale integration," in 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., 2003: IEEE, pp. 372-373.

  145.  M. S. Bakir, H. D. Thacker, Z. Zhou, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of leads microwave characterization and process integration with FEOL and BEOL," in Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No. 02EX519), 2002: IEEE, pp. 116-118.

  146. A. Mule et al., "Optical waveguides with embedded air-gap cladding integrated within a sea-of-leads (SoL) wafer-level package," in Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No. 02EX519), 2002: IEEE, pp. 122-124.

  147. M. S. Bakir, H. A. Reed, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of leads ultra high-density compliant wafer-level packaging technology," in 52nd Electronic Components and Technology Conference 2002.(Cat. No. 02CH37345), 2002: IEEE, pp. 1087-1094.

  148. H. D. Thacker, M. S. Bakir, D. C. Keezer, K. P. Martin, and J. D. Meindl, "Compliant probe substrates for testing high pin-count chip scale packages," in 52nd Electronic Components and Technology Conference 2002.(Cat. No. 02CH37345), 2002: IEEE, pp. 1188-1193.

  149. M. S. Bakir, H. A. Reed, A. V. Mule, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of Leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection," in Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No. 02CH37285), 2002: IEEE, pp. 491-494.

  150. H. A. Reed, M. S. Bakir, C. S. Patel, K. P. Martin, J. D. Meindl, and P. A. Kohl, "Compliant wafer level package (CWLP) with embedded air-gaps for sea of leads (SoL) interconnections," in Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No. 01EX461), 2001: IEEE, pp. 151-153.

  151. A. Naeemi, G. Patel, M. S. Bakir, P. Zarkesh-Ha, K. P. Martin, and J. D. Meindl, "Sea of leads: A disruptive paradigm for a system-on-a-chip (SoC)," in 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No. 01CH37177), 2001: IEEE, pp. 280-281.