HIST Schematic

There is an ever increasing need to integrate multiple dice of various functionalities, including ASICs, CPUs, GPUs, FPGAs, microsensors, photonics, MEMS, and RF components into a single package. This need has spurred significant (perhaps exponential) research in heterogeneous interconnection platforms including 2.5D and 3D. In this thrust, we develop heterogeneous integration architectures that enable the interconnection of multiple dice (or “chiplets”) of various functionalities in a manner that mimics or exceeds monolithic-like performance, yet utilizes advanced off-chip interconnects and packaging to provide flexibility in IC fabrication and design, improved  scalability, reduced development time, and reduced cost. Due to yield, cost, time to market, power dissipation, and performance considerations, 2.5D and 3D heterogeneous integration of chiplets represent a new phase for Moore’s Law. The goal of our research in this thrust is to develop radical new 2.5D and 3D heterogeneous integration architectures for electronics, photonics, and mm-wave technologies. 

Relevant Publications

  1. M. Manley, A. Victor, H. Park, A. Kaul, M. Kathaperumal and M. S. Bakir, "Heterogeneous Integration Technologies for Artificial Intelligence Applications," in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 10, pp. 89-97, 2024, doi: 10.1109/JXCDC.2024.3484958.

  2. T. Zheng and M. S. Bakir, "Electrical Demonstration of an RF Embedded Multichip Module Enabled by Fused-Silica Stitch-Chip Technology," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 14, no. 7, pp. 1172-1179, July 2024, doi: 10.1109/TCPMT.2024.3395538.

  3. A. Victor, M. Manley, S. Oh and M. S. Bakir, "Reconstituted-SiO2 Tier with Integrated Copper Heat Spreader," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 1767-1772, doi: 10.1109/ECTC51909.2023.00302.

  4. T. Zheng and M. S. Bakir, "Benchmarking and Demonstration of Low-Loss Fused-Silica Stitch-Chips With Compressible Microinterconnects for RF/mm-Wave Chiplet-Based Modules," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 13, no. 7, pp. 1064-1066, July 2023, doi: 10.1109/TCPMT.2023.3297023.

  5. T. Zheng, M. Manley and M. Bakir, "Embedded mm-Wave Chiplet Based Module using Fused-Silica Stitch-Chip Technology: RF Characterization and Thermal Evaluation," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 1493-1498, doi: 10.1109/ECTC51909.2023.00253.

  6. A. Kaul, Y. Luo, X. Peng, M. Manley, Y.-C. Luo, S. Yu and M. S. Bakir, "3-D Heterogeneous Integration of RRAM-Based Compute-In-Memory: Impact of Integration Parameters on Inference Accuracy," in IEEE Transactions on Electron Devices, vol. 70, no. 2, pp. 485-492, Feb. 2023, doi: 10.1109/TED.2022.3231570.

  7. T. Zheng and M. S. Bakir, "Benchmarking Frequency-Dependent Parasitics of Fine-Pitch Off-Chip I/Os for 2.5D and 3D Heterogeneous Integration," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 12, pp. 2002-2012, Dec. 2022.

  8. M. Manley, A. Kaul, M. -J. Li and M. S. Bakir, "Ultra-Dense 3D Polylithic Integration Technology", Government Microcircuit Applications & Critical Technology Conf., Miami, FL, Mar. 2022.

  9. J. R. Brescia, J. L. Gonzalez, T. Zheng and M. S. Bakir, "Replaceable Integrated Chiplet (PINCH) Assembly for Heterogeneous Integration", Government Microcircuit Applications & Critical Technology Conf., Miami, FL, Mar. 2022.

  10. T. Zheng, A. Kaul, S. Kochupurackal Rajan, and M. S. Bakir, "Polylithic Integrated Circuits using 2.5D and 3D Heterogeneous Integration: Electrical and Thermal Design Considerations and Demonstrations," in Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces, B. Keser, and S. Kröhnert, Eds. Wiley, 2021, pp. 261-287.

  11. M. -J. Li and M. S. Bakir, "3-D Integrated Chiplet Encapsulation (3-D ICE): High-Density Heterogeneous Integration Using SiO2-Reconstituted Tiers," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 12, pp. 2242-2245, Dec. 2021.

  12. J. L. Gonzalez, J. R. Brescia, T. Zheng, S. Kochupurackal Rajan and M. S. Bakir, "A Die-Level, Replaceable Integrated Chiplet (PINCH) Assembly Using a Socketed Platform, Compressible MicroInterconnects, and Self-Alignment," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 12, pp. 2069-2076, Dec. 2021.

  13. T. Zheng, P. K. Jo, S. Kochupurackal Rajan and M. S. Bakir, "Electrical Characterization and Benchmarking of Polylithic Integration Using Fused-Silica Stitch-Chips With Compressible Microinterconnects for RF/mm-Wave Applications," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 11, pp. 1824-1834, Nov. 2021.

  14. X. Peng, A. Kaul, M. S. Bakir and S. Yu, "Heterogeneous 3-D Integration of Multitier Compute-in-Memory Accelerators: An Electrical-Thermal Co-Design," in IEEE Transactions on Electron Devices, vol. 68, no. 11, pp. 5598-5605, Nov. 2021.

  15. J. L. Gonzalez, S. Kochupurackal Rajan, J. R. Brescia and M. S. Bakir, "A Substrate-Agnostic, Submicrometer PSAS-to-PSAS Self-Alignment Technology for Heterogeneous Integration," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 12, pp. 2061-2068, Dec. 2021.

  16. Y. Hu, M. O. Hossen, Z. Wan, M.S. Bakir, and Y. Joshi, "Compact Transient Thermal Model of Microfluidically Cooled Three-Dimensional Stacked Chips With Pin-Fin Enhanced Microgap," in ASME. J. Electron. Packag., 143(3): 031007, Sep. 2021.

  17. R. Saligram, A. Kaul, M. S. Bakir, and A. Raychowdhury, “Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication,” in A. Calimera, P.-E. Gaillardon, K. Korgaonkar, S. Kvatinsky, R. Reis (Ed.), VLSI-SoC: Design Trends, (1st ed., pp. 149–178) Springer Cham, 2021.

  18. S. Kochupurackal Rajan, A. Kaul, T. E. Sarvey, G. S. May and M. S. Bakir, "Monolithic Microfluidic Cooling of a Heterogeneous 2.5-D FPGA With Low-Profile 3-D Printed Manifolds," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 6, pp. 974-982, June 2021.

  19. A. Kaul, X. Peng, S. Kochupurackal Rajan, S. Yu, and M.S. Bakir, "Thermal Modeling of 3D Polylithic Integration and Implications on BEOL RRAM Performance," in Proc. IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2020. (invited)

  20. R. Saligram, A. Kaul, A. Raychowdhury, and M.S. Bakir, "A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration," in Proc. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), virtual, Salt Lake City, UT, Oct. 2020.

  21. P. Jo, S. Kochupurackal Rajan, J. Gonzalez and M. S. Bakir, "Polylithic Integration of 2.5-D and 3-D Chiplets Enabled by Multi-Height and Fine-Pitch CMIs,"  in IEEE Transactions on Components, Packaging and Manufacturing Technology, Jul.2020.

  22. H. Oh, M. Swaminathan, G. S. May and M. S. Bakir, "Electrical Circuit Modeling and Validation of Through-Silicon Vias Embedded in a Silicon Microfluidic Pin-Fin Heat Sink Filled With Deionized Water," in IEEE Trans. on Comp., Pack. and Manuf. Tech., Aug. 2020.

  23. T. Zheng, P. K. Jo, S. Kochupurackal Rajan, and M. S. Bakir, "Polylithic integration for RF/mm-wave chiplets using stitch-chips: modeling, fabrication, and characterization," 2020 IEEE MTT-S International Microwave Symposium (IMS), Los Angeles, CA, Jun. 2020.

  24. A. Kaul, S. Kochupurackal Rajan, M. O. Hossen, G. S. May, and M. S. Bakir, "BEOL-Embedded 3D Polylithic Integration: Thermal and Interconnection Considerations," 70th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2020.

  25. J. L. Gonzalez, T. Zheng, S. Kochupurackal Rajan, and M. S. Bakir, “Package Testing using a Socketed Heterogeneous 2.5D/3D Integration Module (SHIM) for mm-wave Applications,” Proceedings of the 2020 GOMAC-Tech – Government Microcircuit Applications and Critical Technology Conference, 2020.

  26. M. O. Hossen, B. Chava, G. Van der Plas, E. Beyne and M. S. Bakir, "Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and  μ TSVs," in IEEE Trans. on Electron Devices, Jan. 2020.

  27. S. Kochupurackal Rajan, M. Li, G.S. May, and M.S. Bakir, "High density and low-temperature interconnection enabled by mechanical self-alignment and electroless plating" in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Sendai, Japan, Oct. 2019.

  28. Y. Zhang, M. O. Hossen, and M. S. Bakir, "Power delivery network modeling and benchmarking for emerging heterogeneous integration technologies," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 9, pp. 1825-1834, 2019.

  29. P. K. Jo, T. Zheng, and M. S. Bakir, "Polylithic Integration of 2.5D and 3D Chiplets Using Interconnect Stitching," in Proc. 69th IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May. 2019.

  30. Y. Zhang, X. Zhang, and M. S. Bakir, "Benchmarking Digital Die-to-Die Channels in 2.5-D and 3-D Heterogeneous Integration Platforms," IEEE Transactions on Electron Devices, vol. 65, no. 12, pp. 5460-5467, 2018.

  31. P. K. Jo, T. Zheng, and M. S. Bakir, "Multi-Die Polylithic Integration Enabled by Heterogeneous Interconnect Stitching Technology (HIST)," in 27th IEEE Conf. on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, Oct. 2018.

  32. M. O. Hossen, Y. Zhang, and M. Bakir, "Thermal-Power Delivery Network Co-analysis for Multi-Die Integration", in 27th IEEE Conf. on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, Oct. 2018.

  33. P. K. Jo, M. O. Hossen, X. Zhang, Y. Zhang, and M. S. Bakir, "Heterogeneous Multi-Die Stitching: Technology Demonstration and Design Considerations," in Proc. 68th IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May. 2018.

  34. J. L. Gonzalez, P. K. Jo, R. Abbaspour, and M. S. Bakir, "Flexible Interconnect Design using a Mechanically-focused, Multi-Objective Genetic Algorithm," IEEE Journal of Microelectromechanical Systems, vol. 27, no. 4, pp. 677-685, Aug. 2018.

  35. P. K. Jo, X. Zhang, J. L. Gonzalez, G. S. May, and M. Bakir, "Heterogeneous Multi-Die Stitching Enabled by Fine-Pitch & Multi-Height Compressible MicroInterconnects (CMIs)," IEEE Transactions on Electron Devices, vol. 65, no. 7, pp. 2957-2963, July. 2018.

  36.  H. Oh, X. Zhang, P. K. Jo, G. S. May, and M. S. Bakir, "Monolithic-like heterogeneously integrated microsystems using dense low-loss interconnects," in Proc. IEEE Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Phoenix, AZ, Jan. 2017. (invited).

  37. C. Zhang, H. S. Yang, and M. S. Bakir, "A double-lithography and double-reflow process and application to multi-pitch multi-height mechanical flexible interconnects," Journal of Micromechanics and Microengineering, vol. 27, no. 2, pp. 025014-1-025014-6, Jan. 2017.

  38. T. E. Sarvey, Y. Hu, C. E. Green, P. A. Kottke, D. C. Woodrum, Y. K. Joshi, A. G. Fedorov, S. K. Sitaraman, and M. S. Bakir, "Integrated circuit cooling using heterogeneous micropin-fin arrays for nonuniform power maps," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 10, pp. 1617-1624, Oct.2017

  39. T. E. Sarvey, Y. Zhang, C. Cheung, R. Gutala. A. Rahman, A. Dasu, and M. S. Bakir, "Monolithic integration of a micropin-fin heat sink in a 28 nm FPGA," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 9, pp. 1465-1475, Sep. 2017.

  40. Y. Zhang, T. E. Sarvey, and M. S. Bakir, "Thermal evaluation of 2.5-D integration using bridge-chip technology challenges and opportunities", IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 7, pp. 1101 - 1110, July 2017.

  41. P. K. Jo, M. Zia, J. L. Gonzalez, H. Oh, and M. S. Bakir, "Design, fabrication, and characterization of dense compressible microinterconnects,"IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 7, pp. 1003-1010, May. 2017.

  42. H. Oh, G. May, and M. Bakir, "Heterogeneous integrated microsystems with non-traditional through-silicon via technologies," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 7, no. 4, pp. 502-510, Mar. 2017.

  43. X. Zhang, P. K. Jo, M. Zia, G. May, and M. S. Bakir, "Heterogeneous interconnect stitching technology with compressible microinterconnects for dense multi-die integration," IEEE Electron Device Letters, vol. 38, no. 2, pp. 255-257, Feb. 2017.

  44. Y. Zhang and M. S. Bakir, "Integrated thermal and power delivery network co-simulation framework for single-die and multi-die assemblies", IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 7, no. 3, pp. 434-443, Feb. 2017.

  45. R. Abbaspour, D. K. Brown, and M. S. Bakir, "Fabrication and electrical characterization of sub-micron diameter through-silicon via for heterogeneous three-dimensional integrated circuits," Journal of Micromechanics and Microengineering, vol. 27, no. 2, pp. 025011-1-025011-8, Jan. 2017.

  46.  W. Wahby, T. E. Sarvey, H. Sharma, H. Esmaeilzadeh, and M. S. Bakir, "The impact of 3D stacking on GPU-accelerated deep neural networks an experimental study," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Nov. 2016.

  47. Y. Zhang, X. Zhang, W. Wahby, and M. S. Bakir, "Design considerations for 2.5-D and 3-D integration accounting for thermal constraints," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Nov. 2016.

  48. V. Kumar, H. Oh, X. Zhang, L. Zheng, M. S. Bakir, and A. Naeemi, "Impact of on-chip interconnect on the performance of 3D integrated circuits with through silicon vias Part I," IEEE Transaction on Electron Devices, vol. 63, no. 6, pp. 2503-2509, June 2016

  49. M.Zia, C.Wan, Y. Zhang and M.S. Bakir, “Electrical and photonic off-chip interconnection and system integration,” in Tolga Tekin, Nikos Pleros, Richard Pitwon, and Andreas Hakansson (Ed.), “Optical Interconnects for Data Centers,” (1st Edition p.265-286), Woodhead Publishing, Nov. 2016

  50. X. Zhang, V. Kumar, H. Oh, L. Zheng, G. May, A. Naeemi, and M. S. Bakir, "Impact of on-chip interconnect on the performance of 3D integrated circuits with through silicon vias Part II," IEEE Transactions on Electron Devices, vol. 63, no. 6, pp. 2510-2516, June 2016

  51. W. Wahby and M. S. Bakir, "Impact of Alternate Metals on Routing in Scaled Monolithic 3DICs," in Proc. SRC Techcon, Austin, TX, Sep. 2016.

  52. P. Thadesar and M. S. Bakir, "Fabrication and characterization of polymer-enhanced TSVs, inductors and antennas for mixed-signal silicon interposer platforms," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 6, no. 3, pp. 455-463, Mar. 2016.

  53. M. Zia, C. Zhang, H.S. Yang, L. Zheng and Muhannad Bakir, "Chip-to-chip interconnect integration technologies," IEICE Electron. Express, vol. 13, no. 6, pp. 1-16, Mar. 2016.

  54. H. S. Yang, C. Zhang, and M. S. Bakir, "A self-aligning flip-chip assembly method using sacrificial positive self-alignment structures," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 6, no. 3, pp. 471-477, Feb. 2016.

  55. C. Wan, T. K. Gaylord, and M. S. Bakir, "Rigorous coupled-wave analysis equivalent-index-slab method for analyzing 3D angular misalignment in interlayer grating couplers," Applied Optics, vol. 55, no.35, pp. 10006-10015, Dec. 2016.

  56. M. Zia, T. Chi, J. Park, A. Su, J. L. Gonzalez, P. K. Jo, M. P. Styczynski, H. Wang, and M. S. Bakir, "A 3D integrated electronic microplate platform for lowcost repeatable biosensing applications," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 6, no. 12, pp. 1827-1833, Dec. 2016.

  57. C. Zhang, H. S. Yang, H. D. Thacker, I. Shubin, J. E. Cunningham, and M. S. Bakir, "Mechanically flexible interconnects with contact tip for rematable heterogeneous system integration," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 6, no. 11, pp. 1587-1594, Oct. 2016.

  58. P. Thadesar, X. Gu, R. Alapati and M. S. Bakir, "TSVs: Drivers, performance and innovations (Invited)," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, no. 3, pp. 455-463, July 2016.

  59. X. Liu, P. Thadesar, C. Taylor, M. Kunz, N. Tamura, M. Bakir, and S. Sitaraman, "Experimental stress characterization and numerical simulation for copper pumping analysis of through silicon vias (Invited)," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 6, no. 7, pp. 993-999, July 2016

  60. X. Zhang, V. Kumar, R. Alapati, A. Naeemi and M. S. Bakir, "Interconnect performance in 3D ICs accounting TSV frequency-dependent capacitance and resistive on-chip wires: model, fabrication, and testing," in Proc. SRC Techcon, Austin, TX, Sep. 2015.

  61. . H. Oh, G. May, and M. Bakir, "Silicon interposer platform with low-loss through-silicon vias using air," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Sendai, Japan, Aug. 2015.

  62. Y. Zhang, T. E. Sarvey, and M. S. Bakir, "Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Cork, Ireland, Dec. 2014.

  63. C. Zhang, P. Thadesar, M. Zia, T. E. Sarvey, and M. S. Bakir, "Au-NiW mechanically flexible interconnects (MFIs) for rematable 3D integration," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Cork, Ireland, Dec. 2014.

  64. H. S. Yang, C. Zhang, and M. Bakir, "Self-aligned silicon interposer tiles and silicon bridges using positive self-alignment structures and rematable mechanically flexible interconnects", IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 4, no. 11, pp. 1760-1768, Nov. 2014.

  65. W. Wahby, L. Zheng, Y. Zhang, and M. Bakir, "A virtual integration platform for 3DIC design space exploration," in Proc. SRC Techcon, Austin, TX, Sep. 2014.

  66. H. S. Yang, C. Zhang, and M. Bakir, "Self-aligning silicon interposer tiles and silicon bridges for large nanophotonics enabled systems", Electronics Letters, vol. 50, no. 20, pp. 1475-1477, Sep. 2014.

  67. T. E. Sarvey, Y. Zhang, Y. Zhang, H. Oh, and M. S. Bakir, "Thermal and electrical effects of staggered micropin-fin dimensions for cooling of 3D microsystems,"in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Orlando, FL, May 2014.

  68. C. Zhang, H.S. Yang, M. Bakir, "Mechanically flexible interconnects with highly scalable pitch and large stand-off height for silicon interposer tile and bridge interconnection," in Proc. 64th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2014.

  69. L. Zheng, Y. Zhang, and M. Bakir, "Novel electrical and fluidic microbumps for silicon interposer and 3D-ICs," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 4, no. 5, pp. 777-785, May 2014.

  70. Y. Zhang, A. Dembla, and M. S. Bakir, "Silicon micropin-fin heat sink with integrated TSVs for 3-D ICs: trade-off analysis and experimental testing," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 3, no. 11, pp. 1842-1850, Nov. 2013.

  71. W. Wahby, A. Dembla, and M. Bakir, "Evaluation of 3DICs and fabrication of monolithic interlayer vias," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Oct. 2013.

  72. X. Liu, P. Thadesar, C. Taylor, M. Kunz, N. Tamura, M. Bakir, and S. Sitaraman, "Dimension and liner dependent thermomechanical strain characterization of through-silicon vias using synchrotron x-ray diffraction," Journal of Applied Physics, vol. 114, no. 6, pp. 064908, Aug. 2013.

  73. P. Thadesar and M. Bakir, "Novel photo-defined polymer-enhanced through-silicon vias for silicon interposers," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 3, no. 7, pp. 1130-1137, July 2013.

  74. X. Liu, P. Thadesar, C. Taylor, M. Kunz, N. Tamura, M. Bakir, and S. Sitaraman, "Thermomechanical strain measurements by synchrotron x-ray diffraction and data interpretation for through-silicon vias," Applied Physics Letters , vol. 103, no. 2, pp. 022107-1-022107-5, July 2013.

  75. H.S. Yang, C. Zhang, M.S. Bakir, "A low-cost self-alignment structures for heterogeneous 3D integration," in Proc. 63rd IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May 2013.

  76. L. Zheng, Y. Zhang and M. Bakir, "Design, fabrication and assembly of novel electrical and microfluidic I/Os for 3-D chip stack and silicon interposer," in Proc. 63rd IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May 2013.

  77. P. Thadesar and M. Bakir, "Novel photodefined polymer-embedded vias for silicon interposers," Journal of Micromechanics and Microengineering, vol. 23, no. 3, pp. 035003-1-035003-6, Mar. 2013.

  78. Y. Zhang and M. S. Bakir, "Independent interlayer microfluidic cooling for heterogeneous 3D IC applications," Electronics Letters, vol. 49, no. 6, pp. 404-406, Mar. 2013.

  79. P. Thadesar and M. Bakir, "Silicon interposer featuring novel electrical and optical TSVs," in Proc. ASME International Mechanical Engineering Congress and Exposition, Houston, TX, Nov. 2012.

  80. G. Huang, M. Bakir, A. Naeemi, and J. Meindl, "Power delivery for 3-D chip stacks: physical modeling and design implication," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 2, no. 5, pp. 852-859, May 2012.

  81. H. S. Yang, M. S. Bakir, "Design, fabrication, and characterization of freestanding mechanically flexible interconnects using curved sacrificial layer," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol.2, no.4, pp.561-568, Apr. 2012

  82. B. Dang, M. Bakir, D. Sekar, and J. Meindl, "Single and 3D chip cooling using microchannels and microfluidic chip input/output (I/O) interconnects," IEEE Transaction on Advanced Packaging, vol. 3, no. 1, pp. 79-87, Feb. 2010.

  83. J.-H Lai, H. S. Yang, H. Chen, C. King, J. Zaveri, R. Ravindran, and M. Bakir, "A 'mesh' seed layer for improved through-silicon-via fabrication," Journal of Micromechanics and Microengineering, vol. 20, no. 2, pp. 025016-1-025016-6, Jan. 2010.

  84. M. Bakir, G. Huang, and B. Dang, "3D Integration: Limits and Opportunities," in Coupled Data Techniques, R. Ho and R. Drost (Eds.), Chapter 2, Springer, 2010.

  85. D. Sekar, C. King, B. Dang, M. Bakir, J. Meindl, "Removing heat from 3D stacked chips," Future Fab International, Vol. 29, no. 4, pp. 80-85, Apr. 2009. (invited)

  86. M. Bakir, G. Huang, D. Sekar, and C. King, "3D system integration: power delivery, cooling, and signaling," IETE Technical Review, vol. 26, no. 6, pp. 407-416, 2009. (invited)

  87. M. Bakir and J. Meindl, "Revolutionary Silicon Ancillary Technologies for the Next Era of Gigascale Integration," in Integrated Interconnect Technologies for 3D Nanoelectronic Systems, M. Bakir and J. Meindl (Eds.), Artech House 2009.

  88. M. Bakir and G. Huang, “Power Delivery, Signaling and Cooling for 3D Integrated Systems,” MRS Proceedings, vol. 1156, Jan. 2009.

  89. M. S. Bakir, C. King, D. Sekar, and B. Dang, “Electrical, optical, and fluidic interconnect networks for 3D heterogeneous integrated systems,” 2008 IEEE Avionics, Fiber-Optics and Photonics Technology Conference, Sep. 2008.

  90. C. R. King, D. Sekar, M. S. Bakir, B. Dang, J. Pikarsky, and J. D. Meindl, “3D stacking of chips with electrical and microfluidic I/O interconnects,” 2008 58th Electronic Components and Technology Conference, May 2008.

  91. M. Bakir, A. Glebov, M. Lee, P. Kohl, and J. Meindl, "Mechanically flexible chip-to-substrate optical interconnections using optical pillars," IEEE Transaction on Adv. Packaging, vol. 31, no. 1, pp. 143-153, Feb. 2008.

  92. M. Bakir, B. Dang, O. Ogunsola, R. Sarvari, and J. Meindl, "Electrical and optical chip I/O interconnections for gigascale systems," IEEE Transaction on Electron Devices, vol. 54, no. 9, pp. 2426-2437, Sep. 2007.

  93. O. Ogunsola, H. D. Thacker, B. L. Bachim, M. S. Bakir, J. Pikarsky, T. K. Gaylord, and J. D. Meindl, "Chip-level waveguide-mirror-pillar optical interconnect structure," IEEE Photon. Technol. Lett., vol. 18, no. 15, pp. 1672-1674, Aug. 2006.

  94. K.-N. Chen, M. Bakir, J. Meindl, and R. Reif, "Copper interconnect bonding for polymer pillar I/O interconnects and three-dimensional (3D) integration applications," in Proc. TMS Electronics Materials Conf., 2006.

  95. B. Dang, M. S. Bakir, C. S. Patel, H. D. Thacker, and J. D. Meindl, "Sea-of-Leads MEMS I/O interconnects for low-k IC packaging," IEEE J. Microelectromechanical Systems, vol. 15, no. 3, pp. 523-530, June 2006.

  96. L. Glebov, D. Bhusari, P. Kohl, M. Bakir, J. Meindl, and M. G. Lee, "Flexible pillars for displacement compensation in optical chip assembly," IEEE. Photon. Technol. Lett., vol. 18, no. 6, pp. 974-976, Apr. 2006.

  97. B. Dang, M. S. Bakir, and J. D. Meindl, "Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink," IEEE Electron Device Letters, vol. 27, no. 2, pp. 117-119, Feb. 2006.

  98. M. S. Bakir, B. Dang, R. Emery, G. Vandentop, P. A. Kohl, and J. D. Meindl, "Sea of Leads compliant I/O interconnection process integration for the ultimate enabling of chips with low-k interlayer dielectrics," IEEE J. Adv. Packag., vol. 28, no. 3, pp. 488-494, Aug. 2005.

  99. B. Dang, M. Bakir, K. Martin, and J. Meindl, "Assembly and reliability assessment of Sea-of-Leads compliant wafer level package," in Proceedings IMAPS International Symposium on Microelectronics, 2004, pp 7-14.

  100. K. Shakeri, M. Bakir, and J. D. Meindl, "Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution," in IEEE International SOC Conference, 2004. Proceedings., 2004: IEEE, pp. 78-81.

  101. M. S. Bakir and J. D. Meindl, "Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration," IEEE Transaction Electron Devices, vol. 51, no. 7, pp. 1069-1077, July 2004.

  102. M. S. Bakir, C. O. Chui, A. K. Okyay, K. C. Saraswat, and J. D. Meindl, "Integration of optical polymer pillars chip I/O interconnections with Si MSM photodetectors," IEEE Transaction on Electron Devices, vol. 51, no. 7, pp. 1084-1090, July 2004.

  103. B. Dang, C. Patel, H. Thacker, M. Bakir, K. Martin, and J. Meindl, "Optimal implementation of sea of leads (SoL) compliant interconnect technology," in Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No. 04TH8729), 2004: IEEE, pp. 99-101.

  104. M. S. Bakir and J. D. Meindl, "Integrated electrical, optical, and thermal high density and compliant wafer-level chip I/O interconnections for gigascale integration," in 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No. 04CH37546), 2004, vol. 1: IEEE, pp. 1-6.

  105. M. S. Bakir, B. Dang, R. Emery, G. Vandentop, K. P. Martin, P. A. Kohl, and J. D. Meindl, "Chip integration of sea of leads compliant I/O interconnections for the ultimate enabling of chips with low-k interlayer dielectrics," in 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No. 04CH37546), 2004, vol. 1: IEEE, pp. 1167-1173.

  106. M. S. Bakir, T. K. Gaylord, O. O. Ogunsola, E. G. Glytsis, and J. D. Meindl, "Optical transmission of polymer pillars for chip I/O optical interconnections," IEEE Photon. Technol. Lett., vol. 16, no. 1, pp. 117-119, Jan. 2004.

  107. M. S. Bakir, T. K. Gaylord, K. P. Martin, and J. D. Meindl, "Sea of polymer pillars: compliant wafer-level electrical-optical chip I/O interconnections," IEEE Photon. Technol. Lett., vol. 15, no. 11, pp. 1567-1569, Nov. 2003.

  108. D. C. Keezer, C. S. Patel, M. S. Bakir, Q. Zhou, and J. D. Meindl, "Electrical test strategies for a wafer-level packaging technology," IEEE Trans. Electron. Packag. Manufac., vol. 26, no. 4, pp. 267-272, Oct. 2003.

  109. M. S. Bakir, H. A. Reed, H. D. Thacker, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)," IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2039-2048, Oct. 2003.

  110. M. S. Bakir, R. A. Villalaz, O. O. Ogunsola, T. K. Gaylord, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of polymer pillars: Dual-mode electrical-optical input/output interconnections," in Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No. 03TH8695), 2003: IEEE, pp. 77-79.

  111. M. S. Bakir, T. Gaylord, P. Kohl, K. Martin, and J. Meindl, "Sea of dual mode polymer pillar I/O interconnections for gigascale integration," in 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., 2003: IEEE, pp. 372-373.

  112. M. S. Bakir, H. A. Reed, A. V. Mule, J. Jayachandran, P. A. Kohl, T. K. Gaylord, K. P. Martin, and J. D. Meindl, "Chip-to-module interconnections using 'Sea of Leads' technology," MRS Bulletin, vol. 28, no. 1, pp. 61-67, Jan. 2003. (invited)

  113. A. Mule, M. S. Bakir, J. Jayachandran, R. Villalaz, H. Reed, N. Agrawal, S. Ponoth, J. Plawsky, P. Persans, P. Kohl, K. Martin, E. Glytsis, T. Gaylord, and J. Meindl, "Optical waveguides with embedded air-gap cladding integrated within a sea-of-leads (SoL) wafer-level package," in Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No. 02EX519), 2002: IEEE, pp. 122-124.

  114.  M. S. Bakir, H. D. Thacker, Z. Zhou, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of leads microwave characterization and process integration with FEOL and BEOL," in Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No. 02EX519), 2002: IEEE, pp. 116-118.

  115. M. S. Bakir, H. A. Reed, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of leads ultra high-density compliant wafer-level packaging technology," in 52nd Electronic Components and Technology Conference 2002.(Cat. No. 02CH37345), 2002: IEEE, pp. 1087-1094.

  116. H. D. Thacker, M. S. Bakir, D. C. Keezer, K. P. Martin, and J. D. Meindl, "Compliant probe substrates for testing high pin-count chip scale packages," in 52nd Electronic Components and Technology Conference 2002.(Cat. No. 02CH37345), 2002: IEEE, pp. 1188-1193.

  117. M. S. Bakir, H. A. Reed, A. V. Mule, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of Leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection," in Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No. 02CH37285), 2002: IEEE, pp. 491-494.

  118. J. D. Meindl, R. Venkatesan, J. A. Davis, J. Joyner, A. Naeemi, P. Zarkesh-Ha, M. S. Bakir, T. Mule, P. A. Kohl, and K. P. Martin, "Interconnecting device opportunities for gigascale integration (GSI)," in International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224), 2001: IEEE, pp. 23.1. 1-23.1. 4.

  119. H. A. Reed, M. S. Bakir, C. S. Patel, K. P. Martin, J. D. Meindl, and P. A. Kohl, "Compliant wafer level package (CWLP) with embedded air-gaps for sea of leads (SoL) interconnections," in Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No. 01EX461), 2001: IEEE, pp. 151-153.

  120. A. Naeemi, G. Patel, M. S. Bakir, P. Zarkesh-Ha, K. P. Martin, and J. D. Meindl, "Sea of leads: A disruptive paradigm for a system-on-a-chip (SoC)," in 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No. 01CH37177), 2001: IEEE, pp. 280-281.