lab-member-pic
 

Sreejith Kochupurackal Rajan

  • Ph.D Alumni

 sreejithkrajan@gatech.edu
 
 

Biography

  • Ph.D student in Electrical and Computer Engineering at Georgia Institute of Technology (Advisors Dr. M.S. Bakir and Dr. G.S. May)
  • M.S in Electrical and Computer Engineering at Georgia Institute of Technology , 2016
  • B. Tech. in Electronics and Communication Engineering at Cochin University of Science and Technology (CUSAT), India, 2013

Research Interests

  • Dense die-level and package-level interconnection technologies for heterogenous ICs
  • Thermal management in advanced 2.5D and 3D ICs
  • Heterogenous Integration for healthcare applications

Thesis KOCHUPURACKALRAJAN-DISSERTATION-2022.pdf

All Publications

  1. S. Kochupurackal Rajan, B. Ramakrishnan, H. Alissa, W. Kim, C. Belady and M. S. Bakir, "Integrated Silicon Microfluidic Cooling of a High-Power Overclocked CPU for Efficient Thermal Management," in IEEE Access, vol. 10, pp. 59259-59269, 2022, doi: 10.1109/ACCESS.2022.3179387.

  2. T. Zheng, A. Kaul, S. Kochupurackal Rajan, and M. S. Bakir, "Polylithic Integrated Circuits using 2.5D and 3D Heterogeneous Integration: Electrical and Thermal Design Considerations and Demonstrations," in B. Keser, and S. Kröhnert (Ed.), Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces (pp. 261-287) Wiley, 2021.

  3. J. L. Gonzalez, J. R. Brescia, T. Zheng, S. Kochupurackal Rajan and M. S. Bakir, "A Die-Level, Replaceable Integrated Chiplet (PINCH) Assembly Using a Socketed Platform, Compressible MicroInterconnects, and Self-Alignment," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 12, pp. 2069-2076, Dec. 2021.

  4. T. Zheng, P. K. Jo, S. Kochupurackal Rajan and M. S. Bakir, "Electrical Characterization and Benchmarking of Polylithic Integration Using Fused-Silica Stitch-Chips With Compressible Microinterconnects for RF/mm-Wave Applications," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 11, pp. 1824-1834, Nov. 2021.

  5. J. L. Gonzalez, S. Kochupurackal Rajan, J. R. Brescia and M. S. Bakir, "A Substrate-Agnostic, Submicrometer PSAS-to-PSAS Self-Alignment Technology for Heterogeneous Integration," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 12, pp. 2061-2068, Dec. 2021.

  6. P. Yeon, S. Kochupurackal Rajan, et al., "Microfabrication, Coil Characterization, and Hermetic Packaging of Millimeter-Sized Free-Floating Neural Probes," in IEEE Sensors Journal, vol. 21, no. 12, pp. 13837-13848, 15 June, 2021.

  7. S. Kochupurackal Rajan, A. Kaul, T Sarvey, G. S. May, and M. S. Bakir, "Design Considerations, Demonstration, and Benchmarking of Silicon Micro-cold Plate and Monolithic Microfluidic Cooling for 2.5D ICs," 71st IEEE Electronic Components and Technology Conf. (ECTC),  Jun. 2021.

  8. S. Kochupurackal Rajan, A. Kaul, T. E. Sarvey, G. S. May and M. S. Bakir, "Monolithic Microfluidic Cooling of a Heterogeneous 2.5-D FPGA With Low-Profile 3-D Printed Manifolds," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 6, pp. 974-982, June 2021.

  9. A. Kaul, X. Peng, S. Kochupurackal Rajan, S. Yu, and M.S. Bakir, "Thermal Modeling of 3D Polylithic Integration and Implications on BEOL RRAM Performance," in Proc. IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2020. (invited)

  10. P. Jo, S. Kochupurackal Rajan, J. Gonzalez and M. S. Bakir, "Polylithic Integration of 2.5-D and 3-D Chiplets Enabled by Multi-Height and Fine-Pitch CMIs,"  in IEEE Transactions on Components, Packaging and Manufacturing Technology, Jul.2020.

  11. T. Zheng, P. K. Jo, S. Kochupurackal Rajan, and M. S. Bakir, "Polylithic integration for RF/mm-wave chiplets using stitch-chips: modeling, fabrication, and characterization," 2020 IEEE MTT-S International Microwave Symposium (IMS), Los Angeles, CA, Jun. 2020.

  12. A. Kaul, S. Kochupurackal Rajan, M. O. Hossen, G. S. May, and M. S. Bakir, "BEOL-Embedded 3D Polylithic Integration: Thermal and Interconnection Considerations," 70th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2020.

  13. J. L. Gonzalez, T. Zheng, S. Kochupurackal Rajan, and M. S. Bakir, “Package Testing using a Socketed Heterogeneous 2.5D/3D Integration Module (SHIM) for mm-wave Applications,” Proceedings of the 2020 GOMAC-Tech – Government Microcircuit Applications and Critical Technology Conference, 2020.

  14. S. Kochupurackal Rajan, M. Li, G.S. May, and M.S. Bakir, "High density and low-temperature interconnection enabled by mechanical self-alignment and electroless plating" in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Sendai, Japan, Oct. 2019.

  15. T. E. Sarvey, A. Kaul, S. K. Rajan, A. Dasu, R. Gutala, and M. S. Bakir, "Microfluidic Cooling of a 14-nm 2.5-D FPGA With 3-D Printed Manifolds for High-Density Computing: Design Considerations, Fabrication, and Electrical Characterization," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 12, pp. 2393-2403, 2019.

  16.  P. Yeon, J. L. Gonzalez, M. Zia, S. Kochupurackal Rajan, G. S. May, M. S. Bakir, and M. Ghovanloo, "Microfabrication, Assembly, and Hermetic Packaging of mm-Sized Free-Floating Neural Probes," in Proc. IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, Oct. 2017.